WBUT ECE Sem VII EDA for VLSI Design Question Paper 2008

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West Bengal University of Technology (WBUT) ECE EDA for VLSI Design Question Paper for Sem VIIExam 2008, WBUT Sem VII EDA for VLSI Design Question Papers 2008 For ECE Exam Free Download PDF Previous Year WBUT Sem VII   ECE EDA for VLSI Design Question Bank 2008 Sample Model Question Paper for Students

EDA for VLSI Design
Time Allowed :- 3 hours
Full Marks :- 70

1) Among the following which one has the greatest gate IntegraUon capacity?
a) FPGA b) CPLD
c) PLD d) ASIC.
2) The fastest logic family is
a) TTL b) CMOS
c) ECL d) IIL.
3) The logic family which consumes least amount of power is
a) DTL. b) RCTL
C) CMOS d) none of these.
4. a) What are p-based and k-based designs in VLSI fabricatIon ? In which case full capability of the Fab.Lab. can be utillsed?
b) For 0.5 urn process what Is the value of k? According to the design rule, what will be the minimum widths of diffused region and metal intercoñnect lines?

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